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The basic building blocks are a period-60 gun, a 90-degree glider reflector, a glider duplicator, and a glider eater.Īll the Python code that generates these structures is on GitHub as the sheer size of the machine couldn’t possibly be placed by hand. This means the space between gates is crucial as signals need to be in phase alignment. Because two orthogonal gliders can cancel each other out or form a glider eater if they intersect with a good phase shift, the basic logic gates can be formed from these interactions. Unlike electricity, the Game of Life uses gliders as signals. is one such individual who has created a computer in Conway’s Game of Life. Technically Microsoft PowerPoint, Portal 2, and Magic: the Gathering all are Turing-complete, what of it? Yet, each time someone embarks on an incredible quest of perseverance and creates a computer in one of these mediums, we stand back in awe. We often hear the term “Turing-complete” without giving much thought as to what the implications might be. Posted in FPGA, Games Tagged conways game of life, fpga, game of life

And naturally, this isn’t the first FPGA version of the Game Of Life here at Hackaday. In the future, we’d love to see an even larger FPGA hardware implementation capable of handling grids that could hold whole computers in them. Unfortunately, even this small grid of 60×48 takes up 90% of the LUTs on the Artix-7. Now each pixel in each frame displayed contains over a million generations. Next, instead of connecting the grid logic to the 60 Hz VGA clock, he connects it to the 100 MHz board external oscillator.

Of course, most computers lying around you could simulate a 60 x4 8 grid at 60 fps. Even running at 60 frames per second it’s almost as fast as the monitor can handle. What’s impressive about ’s implementation is just how fast it is. The FPGA chosen for this project is a Digilent Arty A7 with a VGA Pmod to turn the RGB444 into analog signals to actually display. FPGAs already map complex circuits and hardware onto LUTs and other slices, so what’s another layer of abstraction? Chisel and other newer HDL languages focus on expressing high-level general-purpose elements that get mapped onto hardware. In broad strokes, Verilog and VHDL are focused on expressing hardware and then added abstraction on top of that over the year.
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Under the hood, Chisel is Scala with some custom libraries that know how to map Scala concepts onto hardware. ’s version uses Chisel, a new HDL from the Berkley and RISCV communities. set out to turn that on its head by implementing Game Of Life in the hardware of an FPGA. The usual approach is to just iterate over every cell in the grid, computing the next state into a new grid buffer. Munged Ferris Bueller quotes aside, Conway’s Game of Life is the classic cellular automata that we all reach for.
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We can’t get enough of our calculator hacks here, so make sure to check out the CPU transplant on this vintage Soviet calculator.Ĭontinue reading “Old Casio Calculator Learns New Tricks” → Posted in classic hacks, Software Hacks Tagged assembly, calculator, casio, conways game of life, forth, game of life He also managed to get a version of Conway’s Game Of Life running, check out the video after the break. ended up porting a Forth interpreter, which defaults to RPN style, to finally achieve his humble objective. With RAM to burn, new routines were created to write custom characters to the screen, and a new font was created to squeeze more characters onto the display than normal.

Here, the contents of RAM could be easily modified with custom code, then uploaded back into the calculator. With 32KB of RAM there ended up being plenty of room for experimentation, and uploading a program into RAM was simplified by using Casio’s original backup software to dump the RAM onto a PC. With the entire calculator emulated in software, the plan from here involved replacing one of the BASIC commands in ROM with new code that would jump to an address in RAM. Incredibly, the MAME framework already featured a ‘partial implementation’ of the calculator’s CPU, which was a much needed shot in the arm when it came time to write a full-featured emulator. The first step in cracking this calculator wide open was a ROM dump, followed by writing a disassembler. An RPN interpreter written in assembly language would be much faster. The calculator in question can already run its own version of BASIC, however the bespoke Hitachi CPU struggles performance-wise with complex programs, and wouldn’t be a realistic way of using RPN on the calculator.
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Needing a project to keep him occupied, he decided to upgrade his 90s Casio CFX-9850G calculator to run custom machine code.Īll really wanted was for his vintage calculator to understand Reverse Polish Notation (RPN).
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Recently found himself stung by the burden of free time while in lockdown.
